The present invention relates to a technology effectively applicable to a high-speed convergence of a PLL circuit, which converts an IF (Intermediate Frequency) signal into a RF (Radio Frequency) signal.
There exist some systems in a transmitter used for mobile station. The most popular system is a mixer system which is constructed in a manner of converting a base band signal into an IF (Intermediate Frequency) signal by a modulator, and converting the IF signal into a frequency to be transmitted from an antenna by a mixer. Besides, there is a PLL system, which makes a frequency conversion by using a PLL circuit in place of the above mixer used in the system. The PLL system has a demerit of treating only modulation with constant envelop; however, the PLL system has a merit of greatly reducing a transmission noise as compared with the mixer system. Thus, the PLL system is used for a wireless mobile station of a GSM (Global System for Mobile communications) system. The operating principle has been described in detail in IEEE journal of solid-state circuits Vol. 32, No. 12, pp. 2089-2096, xe2x80x9cA 2.7-V GSM RF Transceiver ICxe2x80x9d, for example.
FIG. 12 is a view showing a construction of the PLL circuit used in the PLL system. The PLL circuit is composed of a phase comparator 100 with current mode output, a constant current source 101, a mixer 105, a low-pass filter (LPF) 103, a voltage-controlled oscillator (VCO) 104, and a switch (SW) 102. In the following description, it is assumed that the VCO 104 has a positive sensitivity. In general, as the LPF 103, a secondary LPF comprising a passive element as shown in FIG. 12 is used. Moreover, a control signal LOGIC1 is given to the switch SW 102. In the case where the LOGIC1 is zero xe2x80x9c0xe2x80x9d, the switch SW 102 becomes an open state; on the other hand, in the case where the LOGIC1 is xe2x80x9c1xe2x80x9d, the switch SW 102 is short-circuited to ground.
As the phase comparator 100 with current mode output, a high-speed operable phase comparator with mixer is used, and not a phase frequency comparator, and thereby, it is possible to improve a degree of freedom in frequency construction of a transmitter. The phase comparator has a problem such that in the case where a difference between two input frequencies is great, an output voltage is suppressed by the LPF 103; as a result, no output voltage is transmitted to the VCO 104. In other words, the PLL circuit is not converged depending upon an output frequency from the VCO 104 in the initial convergence state. In order to solve the above problem, the constant current source 101 and the switch SW 102 are connected. Before the PLL circuit is converged, the SW 102 is necessarily connected to ground so as to set an input voltage of the VCO 104 to a ground voltage. Thereafter, the switch SW 102 is opened so as to start convergence. Even in the case where no output of the phase comparator 100 with current mode output is transmitted to the VCO 104, the constant current source 101 charges the capacity of the LPF 103, and thereby, an input voltage of the VCO 104 increases. By doing so, two input frequencies of the phase comparator 100 with current mode output can approach each other. When these two input frequencies sufficiently approach each other, the output of the phase comparator 100 with current mode output is transmitted to an input of the VCO 104; therefore, convergence is possible.
In the GSM system, a TDMA (Time Division Multiple Access) system is used. One frame is 120/26 ms, and is composed of eight time slots of 15/26 ms. One slot is used for reception, and another slot is used for transmission. FIG. 13 is a view showing one example of reception and transmission timing of a mobile station. In this example, a time slot 1 is allocated to reception, and a time slot 4 is allocated to transmission. A reception-transmission interval is equivalent to a period of two time slots. However, in this case, considering a delay from the mobile station to a base station, the transmission is early made by a timing advance of 3024/13 xcexcs to the maximum.
The following is a description on an operation of the above PLL system according to the TDMA system of the GSM. The operation of the PLL system will be described below with reference to the conventional PLL circuit and a timing chart shown in FIG. 14. For convenience of explanation, an input center frequency of the phase comparator 100 with current mode output is set as 270 MHz, and a frequency of local oscillator signal LO inputted to the mixer 105 is set as 1180 MHz. Moreover, an input sensitivity of the VCO 104 is positive, and an output frequency thereof is set as 850 MHz when an input voltage is 0V. In the case where the mobile station is not in a transmission timing state, xe2x80x9c1xe2x80x9d, is inputted to the LOGIC1, and therefore, the output of the phase comparator 100 with current mode output becomes 0V. Whereby an electric charge stored in the capacity of LPF 103 is discharged, and therefore, the input voltage of the VCO 104 becomes 0V, too. Thus, an output frequency of the VCO 104 becomes 850 MHz. When a time t1 comes, xe2x80x9c0xe2x80x9d is inputted to the LOGIC1, and the SW 102 becomes an open state. At that time, an output frequency of the mixer 105 is the sum and the difference between 850 MHz and 1180 MHz, that is, 2030 MHz and 330 MHz. The sum component is suppressed by the LPF 103, and does not contribute to convergence; for this reason, only difference component is considered in this case. Therefore, the output frequency of the phase comparator 100 with current mode output becomes 60 MHz (=330xe2x88x92270). In the case of applying the PLL circuit to the GSM system, in general, the loop bandwidth of the PLL circuit is designed to be around 1 MHz; for this reason, an output signal of the mixer 105 is sufficiently suppressed by the LPF 103. Thus, the output signal does not contribute for storing an electric charge to the capacity of the LPF 103. Namely, feedback becomes an off state. However, an electric charge is stored in the capacity of the LPF 103 by a constant current from the constant current source 101, so that an input voltage of the VCO 104 can be increased. As a result, the output frequency of the VCO 104 gradually increases from 850 MHz. For example, in the case where the input voltage of the VCO 104 increases to 908 MHz, at that time, an output frequency of the phase comparator 100 with current mode output becomes 2 MHz. Therefore, the suppression by the LPF 103 is decreased, and this can contribute for storing an electric charge to the capacity of the LPF 103. Namely, a recovery of feedback is made. The recovery of feedback is made, and thereby, the PLL circuit is finally converged, and then, the output frequency of the VCO 104 becomes 910 MHz (=1180xe2x88x92270). The convergence must be completed earlier than a time t2 when a transmitting period starts. At a time t3 when the transmitting period ends, xe2x80x9c1xe2x80x9d is inputted to the LOGIC1, and then, the input voltage of the VCO 104 again becomes 0V in preparation for the next transmitting period.
FIG. 15 is a view showing a change of input voltage of the VCO 104 in the above convergence process. The input voltage of the VCO 104 is 0V by the time t1. The switch SW 102 becomes an open state at the time t1, and then, the input voltage starts to increase linearly. An inclination of the increase is determined mainly by an output current I1 of the constant current source 101 and the total capacity C of the LPF 103, and therefore, is obtained from a relation of I1/C. Thereafter, the recovery of feedback is made, and the convergence is completed. Assuming that a sensitivity of the VCO 104 is set as Kv, the output frequency of the VCO 104 is set as f0 when its input voltage is 0V, the output frequency of the VCO 104 in convergence is set as f1, the input voltage V1 in convergence is obtained from the following equation (1).
V1=(f1xe2x88x92f0)/Kvxe2x80x83xe2x80x83(1) 
A convergence time ts of the PLL circuit approximates to a time until the total capacity C is charged to V1 by the output current I1; therefore, the convergence time ts is obtained from the following equation (2).
ts=(f1xe2x88x92f0)/Kvxc2x7C/I1xe2x80x83xe2x80x83(2) 
Therefore, the higher f1 is, the longer the convergence time becomes. For example, in the GSM system, the convergence time becomes the longest when a transmitting frequency is converged to the maximum usable frequency 915 MHz.
In recent years, a demand for high-speed data communication services has rapidly risen. With the demand, in the GSM system, some systems for improving a conventional data rate have been proposed, and research and development have been made for practical use. One of the high-speed data communication services is a GPRS (General Packet Radio Service). The GPRS is a system of allocating a plurality of time slots to transmission or reception so as to improve a data rate, as shown in FIG. 16. As is evident from a comparison between FIG. 13 and FIG. 16, in the GPRS, a time usable to the convergence of PLL circuit is about half of the conventional GSM system. For this reason, there is a need of shortening the convergence time of the PLL circuit.
As described before, the convergence time ts of the conventional PLL circuit is obtained from the above equation (2). In order to shorten the convergence time ts, there is a need of changing a parameter included in the above equation (2). In general, the VCO 104 is provided as a module component; therefore, its characteristic values, that is, f0 and Kv are a fixed value. Moreover, it is difficult to freely change I1/C due to the following limiting conditions 1) and 2).
1) A ratio of output current of the phase comparator 100 with current mode output to C is determined by a modulation bandwidth and an allowed noise level used as a system parameter.
2) A convergence stability of the PLL circuit is determined by a ratio of the output current to I1.
Namely, in the case of the conventional PLL circuit, it is difficult to shorten the convergence time while satisfying the above limiting conditions.
It is, therefore, an object of the present invention to shorten the maximum convergence time of a conventional PLL circuit while satisfying the above limiting conditions.
The above, other objects and novel constituent features of the present invention will be more apparent from the description of the present specification and the accompanying drawings.
The following is a brief description on an outline of disclosures of the present invention.
In order to achieve the above object, a PLL circuit of the present invention comprises at least: a phase comparator with current mode output; a low-pass filter; and a VCO. The PLL circuit sets an input voltage of the VCO as 0V before convergence start, and in the case where a convergence frequency of the PLL circuit is lower than a setting frequency, converges the input voltage by a PLL feedback loop within a range from 0V to a convergence voltage. Moreover, in the case where the convergence frequency of the PLL circuit is higher than the setting frequency, the PLL circuit increases the input voltage from 0V to a power-supply voltage by using no PLL feedback loop, and thereafter, converges the input voltage by the PLL feedback loop within a range from the power-supply voltage to the convergence voltage.
Further, as other operations for achieving the above object, a PLL circuit of the present invention comprises at least: a phase comparator with current mode output; a low-pass filter; and a VCO. The PLL circuit sets an input voltage of the VCO as a power-supply voltage before convergence start, and in the case where a convergence frequency of the PLL circuit is higher than a setting frequency, converges the input voltage by a PLL feedback loop within a range from the power-supply voltage to a convergence voltage. Moreover, in the case where the convergence frequency of the PLL circuit is lower than the setting frequency, the PLL circuit drops the input voltage from the power-supply voltage to 0V by using no PLL feedback loop, and thereafter, converges the input voltage by the PLL feedback loop within a range from 0V to the convergence voltage.
Further, in order to achieve the above object, a PLL circuit of the present invention comprises: a phase comparator with current mode output, for outputting a signal proportional to a phase difference between first input signal modulated in its frequency and second input signal; an LPF connected to an output terminal of the phase comparator with current mode output; a VCO connected to an output terminal of the low-pass filter; a mixer connected to an output terminal of the VCO and converting an output frequency of the VCO so as to output a second signal; first and third constant current sources for outputting a constant current to the output terminal of the phase comparator with current mode output; a second constant current source for inputting a constant current from the output terminal of the phase comparator with current mode output, a first switch connected between the phase comparator with current mode output and a ground and control means for controlling an on-off of the first to third constant current sources and a short-circuit and open of the first switch.
Further, as other structures for achieving the above object, in the PLL circuit of the present invention, the third constant current source is replaced with a second switch connected between an output terminal of the phase comparator with current mode output and a power-supply voltage, and means for controlling an on-off of the second switch is additionally provided.
Further, as other structures for achieving the above object, in the PLL circuit of the present invention, the first and third constant current sources are replaced with a variable current source, and means for controlling an on-off and output current value of the variable current source is additionally provided.
Further, in order to achieve the above object, a wireless mobile station of the present invention comprises: a base band circuit; a modulator for inputting a first base band signal from the base band circuit; a PLL circuit connected to an output of the modulator; a power amplifier connected to an output of the PLL circuit; a receiver circuit for outputting a second base band signal to the base band circuit; an antenna; and a selector connected with the antenna, an input of the receiver circuit and an output of the power amplifier, the base band circuit outputting a control signal for controlling an operation of the wireless mobile station, the PLL circuit comprising the PLL circuit described before. Moreover, the selector is an antenna switch or duplexer.